Signal processing apparatus, method and program

ABSTRACT

An apparatus including a one-field delay circuit  21  for delaying a luminance signal F 0  of a video signal under judgment by an amount of one field; a subtractor circuit  22  for generating a difference signal FD 0  indicating the difference between a luminance signal F 1  and the luminance signal F 0  for each field; an adder circuit  23 ; a one-field delay circuit  24 ; a one-field delay circuit  25  for delaying the difference signal FD 0  by an amount of one field; and a comparison circuit  26  and a judgment circuit  27  for comparing the difference signals FD 0  and FD 1  and deciding if the luminance signal FD 0  is a film video signal based on the result of the comparison.

TECHNICAL FIELD

The present invention relates to a signal processing apparatus andmethod and a program, more particularly relates to a signal processingapparatus capable of judging a format of a signal by a simpleconfiguration, a method of the same, and a program of the same.

BACKGROUND ART

In order to view a video signal in a state with little flicker, recentlythe practice of converting a video signal of the interlace method to avideo signal of the progressive method has become prevalent.

A video signal of the NTSC (National Television System Committee) methodis comprised of 60 fields (30 frames) per second. As opposed to this, ina signal obtained from a movie film, the number of frames per second ismade 24 frames. Accordingly, when converting an image of a movie to avideo signal of the NTSC method, the conversion processing is carriedout by the 3-2 pull-down method. When this conversion processing iscarried out, images of the same frame are arranged in two continuousfields, and the same images of the next frame are arranged in thefollowing three continuous fields. As a result, images of 24 frames canbe assigned to 60 fields.

In this way, in a 3-2 pull-down converted film video signal, the videosignals of the first field and the third field among three continuousfields become exactly the same video signals. When converting a videosignal of the interlace method to a video signal of the progressivemethod, if the same video signal has been already encoded, theprocessing of the video signal appearing second can be omitted.Accordingly, when it is known in advance whether or not the video signalis a film video signal, more efficient encoding becomes possible.

Therefore, a method of judging whether or not a video signal is a 3-2pull-down converted film video signal is disclosed in for example U.S.Pat. No. 4,982,280.

FIG. 11 shows the principle of the method proposed in this U.S. Patent.As shown in the figure, a video signal consists of a signal in which odd(O) and even (E) fields alternately appear. In the case of a 3-2pull-down converted video signal, the image (luminance signal) of thefirst frame A is defined as the video signal of two fields of an oddfield Ao and an even field Ae.

The image of the next frame B is arranged in three fields of an oddfield, an even field, and a next odd field. Namely, the first field isdefined as the odd field Bo, the next field is defined as the even fieldBe, and the third field is defined as the odd field Bo. Accordingly,among three fields, the first odd field Bo and the third odd field Bobecome exactly the same signal.

Below, video signals of frames of a film such as a frame C, a frame D, aframe E, and a frame F are assigned to fields of the video signals inthe same way as above.

When now assuming that an original signal which is not delayed among theluminance signals is F0, this original signal F0 is delayed by theamount of one field to obtain a signal F1. This signal F1 is furtherdelayed by the amount of one field to obtain a signal F2.

Looking at the value of the frame reference obtained by subtracting thesignal F2 from the signal F0, as shown in FIG. 11, the values of thesignals F0 and F2 become the same at Bo, De, Fo, He, . . . at least onetime in each cycle consisting of five fields. As a result, the value ofF0-F2 becomes 1101111011110 . . . Namely, defining five fields as theperiod, the value becomes 0 at least one time in each cycle.

Contrary to this, in the case of a video signal of the ordinary NTSCmethod not a 3-2 pull-down converted video signal, the frame referencebecomes 11111111 . . .

Accordingly, it can be judged whether or not a video signal is a filmvideo signal from the difference of patterns of the frame differences.

When judging if a signal is a film video signal, however, it isnecessary to provide two one-field delay circuits of the one-field delaycircuit for generating the signal F1 and the one-field delay circuit forgenerating the signal F2, so the apparatus becomes large in scale. Thesame problem occurs also in a case of detecting a detected signalcomprised of a plurality of module signals where there is a pattern oftwo coinciding module signals located on two sides sandwiching apredetermined module signal at a predetermined position in apredetermined number of continuous module signals.

DISCLOSURE OF THE INVENTION

The present invention was made in consideration with such a circumstanceand has as an object thereof to provide a signal processing apparatuscapable of being reduced in scale when detecting a video signal in whichthere is a pattern of two coinciding fields located on two sidessandwiching a predetermined field at a predetermined position in apredetermined number of continuous fields, a method of the same, and aprogram of the same.

Further, the present invention has as its object to provide a signalprocessing apparatus capable of being reduced in scale when detecting adetected signal comprised of a plurality of module signals wherein thereis a pattern of two coinciding module signals located on two sidessandwiching a predetermined module signal at a predetermined position ina predetermined number of continuous module signals

To attain the above object, according to a first aspect of theinvention, there is provided a signal processing apparatus comprising afirst delaying means for delaying a luminance signal by an amount of onefield; a processing means for generating a difference signal indicatinga difference between the luminance signal delayed by an amount of onefield by the first delaying means and a not delayed luminance signal foreach field; a second delaying means for delaying the difference signalgenerated by the processing means by an amount of one field; and ajudging means for comparing the difference signal generated by theprocessing means and the difference signal delayed by an amount of onefield by the second delaying means and judging the format of theluminance signal based on the result of the comparison.

The mode of operation of the signal processing apparatus of the firstaspect of the invention is as follows.

The first delaying means delays a luminance signal by an amount of onefield.

Then, the processing means generates a difference signal indicating thedifference between the luminance signal delayed by an amount of onefield by the first delaying means and a not delayed luminance signal foreach field.

Then, the second delaying means delays the difference signal generatedby the processing means by an amount of one field.

Then, the judging means compares the difference signal generated by theprocessing means and the difference signal delayed by an amount of onefield by the second delaying means and judges the format of theluminance signal based on the result of the comparison.

In the signal processing apparatus of the first aspect of the invention,preferably, the processing means finds the difference in units of pixeldata in each field and generates the difference signal defining thevalue obtained by cumula tively adding one-field amounts of thedifferences as the difference of the fields.

Further, in the signal processing apparatus of the first aspect of theinvention, preferably the judging means judges that the luminance signalis a film video signal when the difference signal generated by theprocessing means and the difference signal delayed by an amount of onefield by the second delaying means coincide at an interval correspondingto the time of a predetermined number of fields based on the result ofthe comparison.

Further, in the signal processing apparatus of the first aspect of theinvention, preferably the film video signal is a film video signal inwhich there is a pattern of coinciding luminance signals of two fieldslocated at two sides sandwiching a luminance signal of a predeterminedfield at a predetermined position in a predetermined number ofcontinuous fields.

Further, in the signal processing apparatus of the first aspect of theinvention, preferably the apparatus is further provided with a thirddelaying means for delaying the luminance signal delayed by an amount ofone field by the first delaying means further by the amount of one fieldand a signal generating means for generating a progressive signal bycombining line signals in the not delayed luminance signal, theluminance signal delayed by the first delaying means, and the luminancesignal delayed by the third delaying means based on the result ofjudgment of the judging means.

According to a second aspect of the invention, there is provided asignal processing method comprising a first step of delaying a luminancesignal by an amount of one field; a second step of generating adifference signal indicating the difference between the luminance signaldelayed by an amount of one field at the first step and a not delayedluminance signal for each field; a third step of delaying the differencesignal generated at the second step by an amount of one field; and afourth step of comparing the difference signal generated at the secondstep and the difference signal delayed by an amount of one field at thethird step and judging the format of the luminance signal based on theresult of the comparison.

According to a third aspect of the invention, there is provided aprogram executed by a signal processing apparatus, comprising a firstroutine of delaying a luminance signal by an amount of one field; asecond routine of generating a difference signal indicating thedifference between the luminance signal delayed by an amount of onefield in the first routine and a not delayed luminance signal for eachfield; a third routine of delaying the difference signal generated inthe second routine by an amount of one field; and a fourth routine ofcomparing the difference signal generated in the second routine and thedifference signal delayed by an amount of one field in the third routineand judging the format of the luminance signal based on the result ofthe comparison.

According to a fourth aspect of the invention, there is provided asignal processing apparatus for detecting a detected signal comprised ofa plurality of module signals wherein there is a pattern of twocoinciding module signals located at two sides sandwiching apredetermined module signal at a predetermined position in apredetermined number of continuous module signals, comprising a firstdelaying means for delaying a signal under detection by an amount of onemodule signal; a processing means for generating a difference signalindicating the difference between the signal under detection delayed byan amount of one module signal by the delaying means and a not delayedsignal under detection in units of the module signal; a second delayingmeans for delaying the difference signal generated by the processingmeans by an amount of one module signal; and a detecting means forcomparing the difference signal generated by said processing means andsaid difference signal delayed by an amount of one module signal by saidsecond delaying means and detecting whether or not said signal underdetection is said detected signal based on the result of the comparison.

The mode of operation of the signal processing apparatus of the fourthaspect of the invention is as follows.

The first delaying means delays a signal under detection by an amount ofone module signal.

Then, the processing means generates a difference signal indicating thedifference between the signal under detection delayed by an amount ofone module signal by the first delaying means and a not delayed signalunder detection in units of the module signal.

Then, the second delaying means delays the difference signal generatedby the processing means by an amount of one module signal.

Then, the detecting means compares the difference signal generated bythe processing means and the difference signal delayed by an amount ofone module signal by the second delaying means and detects whether ornot the signal under detection is the detected signal based on theresult of the comparison.

According to a fifth aspect of the invention, there is provided a signalprocessing method for detecting a detected signal comprised of aplurality of module signals wherein there is a pattern of two coincidingmodule signals located at two sides sandwiching a predetermined modulesignal at a predetermined position in a predetermined number ofcontinuous module signals, comprising a first step of delaying a signalunder detection by an amount of one module signal; a second step ofgenerating a difference signal indicating the difference between thesignal under detection delayed by an amount of one module signal at thefirst step and a not delayed signal under detection in units of themodule signal; a third step of delaying the difference signal generatedat the second step by an amount of one module; and a fourth step ofcomparing the difference signal generated at the second step and thedifference signal delayed by an amount of one module signal at the thirdstep and detecting whether or not the signal under detection is thedetected signal based on the result of the comparison.

According to a sixth aspect of the invention, there is provided aprogram, executed by a signal processing apparatus, for detecting adetected signal comprised of a plurality of module signals wherein thereis a pattern of two coinciding module signals located on two sidessandwiching a predetermined module signal at a predetermined position ina predetermined number of continuous module signals, comprising a firstroutine of delaying a signal under detection by an amount of one modulesignal; a second routine of generating a difference signal indicatingthe difference between the signal under detection delayed by an amountof one module signal in the first routine and the not delayed signalunder detection in units of the module signal; a third routine ofdelaying the difference signal generated in the second routine an amountof one module; and a fourth routine of comparing the difference signalgenerated in the second routine and the difference signal delayed by anamount of one module signal in the third routine and detecting whetheror not the signal under detection is the detected signal based on theresult of the comparison.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of a signal processing apparatus ofa first embodiment of the present invention.

FIGS. 2A to 2E are views for explaining signals shown in FIG. 1 in acase where a luminance signal F0(Y) of a 3-2 pull-down converted filmvideo signal is input to the signal processing apparatus shown in FIG.1.

FIG. 3 is a flow chart for explaining an example of the operation of thesignal processing apparatus shown in FIG. 1.

FIG. 4 is a functional block diagram of a DVD player according to asecond embodiment of the present invention.

FIGS. 5A to 5J are views for explaining signals of the DVD player shownin FIG. 4.

FIG. 6 is a diagram for explaining the processing of a time axiscompression circuit and a selector circuit in a latter stage shown inFIG. 4.

FIG. 7 is a view for explaining the processing of the time axiscompression circuit and the selector circuit in the latter stage shownin FIG. 4.

FIG. 8 is a view for explaining the processing of the time axiscompression circuit and the selector circuit in the latter stage shownin FIG. 4.

FIG. 9 is a view for explaining the processing of the time axiscompression circuit and the selector circuit in the latter stage shownin FIG. 4.

FIG. 10 is a view for explaining a third embodiment of the presentinvention.

FIG. 11 is a view for explaining the prior art.

BEST MODE FOR WORKING THE INVENTION

Below, an explanation will be given of signal processing apparatusesaccording to embodiments of the present invention.

[First Embodiment]

FIG. 1 is a functional block diagram of a signal processing apparatus 20of the present embodiment.

As shown in FIG. 1, the signal processing apparatus 20 has for example aone-field delay circuit 21, a subtractor circuit 22, an adder circuit23, one-field delay circuits 24 and 25, a comparison circuit 26, and ajudgment circuit 27.

Here, the one-field delay circuit 21 corresponds to the first delayingmeans of the present invention, the subtractor circuit 22 and the addercircuit 23 correspond to the processing means of the present invention,the one-field delay circuit 25 corresponds to the second delaying meansof the present invention, and the subtractor circuit 22 and the judgmentcircuit 27 correspond to the judging means or the detecting means of thepresent invention.

FIGS. 2A to 2E are views for explaining signals shown in FIG. 1 in acase where a luminance signal F0(Y) of a 3-2 pull-down converted filmvideo signal explained before by using FIG. 11 is input to the signalprocessing apparatus 20.

As shown in FIGS. 2A to 2E, in the luminance signal of the film videosignal, when viewing continuous luminance signals of five fields (forexample, Ao, Ae, Bo, Be, Bo), there are luminance signals Bo and Bo oftwo fields located at two sides sandwiching a luminance signal of thesecond field. Further, in the luminance signal F0, there is thiscoinciding pattern at the same position in the five continuous fields.

Note that the signal of each field corresponds to the module signal ofthe fourth aspect of the invention.

Accordingly, in the difference signal F0 indicating the differencebetween the luminance signal F1 obtained by delaying the luminancesignal FD0 by one field and the luminance signal F0, d2 indicating thedifference between the third Be and the fourth Bo, and d3 indicating thedifference between the fourth Bo and the fifth Be coincide (become thesame). In the signal processing apparatus 20 of the present embodiment,it is judged whether or not the input luminance signal is a film videosignal by detecting the coincidence.

This film video signal is a signal obtained by converting for example afilm material of 24 frames/second to a 60 Hz interlace signal by the 3-2pull-down processing.

Below, an explanation will be given of components of the signalprocessing apparatus 20 by referring to FIG. 1 and FIGS. 2A to 2E.

The one-field delay circuit 21 outputs the luminance signal F1, obtainedby delaying the input luminance signal F0(Y) shown in FIG. 2A by anamount of one field, to the subtractor circuit 22.

The subtractor circuit 22 generates a difference signal S22 indicating avalue obtained by finding the difference between the not delayedluminance signal F0 and the luminance signal F1 shown in FIG. 2B delayedby an amount of one field input from the one-field delay circuit 21 inunits of the pixel data in each field and outputs this to the addercircuit 23.

The adder circuit 23 generates a difference signal S23 indicating avalue obtained by cumulatively adding the differences indicated by thedifference signal S22 from the subtractor circuit 22 for each field andoutputs this to the delay circuit 24.

The one-field delay circuit 24 outputs the difference signal FD0 shownin FIG. 2C obtained by delaying the difference signal S23 input from theadder circuit 23 by an amount of for example one field to the one-fielddelay circuit 25 and the comparison circuit 26.

The one-field delay circuit 25 outputs the difference signal FD1 shownin FIG. 2D, obtained by delaying the difference signal FD0 input fromthe one-field delay circuit 24 by an amount of one field, to thecomparison circuit 26.

The comparison circuit 26 compares the difference signals FD0 and FD1 inunits corresponding to each field, generates a comparison result signalCOMP shown in FIG. 2E indicating a logical value “1” (first logicalvalue) at a timing when they coincide and indicating a logical value “0”(second logical value) at a timing when they do not coincide; andoutputs this to the judgment circuit 27.

Specifically, the comparison circuit 26 computes the difference betweenthe difference signals FD0 and FD1 in units corresponding to each field,decides whether or not the difference is larger than a predeterminedreference value, makes the value of the comparison result signal COMP ina corresponding field period the logical value “0” when deciding thatthe difference is larger, and makes the value of the comparison resultsignal COMP in the corresponding field period the logical value “1” whendeciding that the difference is smaller.

At this time, when the luminance signal F0 is a luminance signal of afilm video signal, the comparison result signal COMP periodicallygenerates a pulse of the logical value “1” one time per five fields bythe format of the film video signal explained by using FIG. 11.

Note that when the luminance signal F0 is a signal after A/D conversionetc., there is a case where the signals of different fields obtainedfrom the same material in the luminance signal F0 will not completelycoincide due to the influence of noise etc., therefore the decision ofcoincidence/non-coincidence by the comparison circuit 26 is carried outconsidering this.

The judgment circuit 27 judges whether or not the video signalcorresponding to the luminance signal F0 is a film video signal and thesequence thereof based on the comparison result signal COMP from thecomparison circuit 26.

Specifically, the judgment circuit 27 judges that the luminance signalF0 is a luminance signal of a film video signal when deciding that thecomparison result signal COMP periodically generates a pulse of thelogical value “1” one time in five fields.

Below, an explanation will be given of an example of the operation ofthe signal processing apparatus 20 shown in FIG. 1.

FIG. 3 is a flow chart for explaining the example of operation.

Step ST1:

The one-field delay circuit 21 outputs a luminance signal F1, obtainedby delaying the input luminance signal F0(Y) shown in FIG. 2A by anamount of one field, to the subtractor circuit 22.

Step ST2:

The subtractor circuit 22 generates a difference signal S22 indicating avalue obtained by finding the difference between the not delayedluminance signal F0 and the luminance signal F1 shown in FIG. 2B delayedby an amount of one field input from the one-field delay circuit 21 inunits of the pixel data in each field and outputs this to the addercircuit 23.

Step ST3:

The adder circuit 23 generates a difference signal S23 indicating avalue obtained by cumulatively adding the differences indicated by thedifference signal S22 from the subtractor circuit 22 for each field andoutputs this to the one-field delay circuit 24.

Then, the one-field delay circuit 24 outputs the difference signal FD0shown in FIG. 2C, obtained by delaying the difference signal S23 inputfrom the adder circuit 23 by an amount of one field, to the one-fielddelay circuit 25 and the comparison circuit 26.

Step ST4:

The one-field delay circuit 25 outputs the difference signal FD1 shownin FIG. 2D obtained by delaying the difference signal FD0 input from theone-field delay circuit 24 by an amount of one field to the comparisoncircuit 26.

Step ST5:

The comparison circuit 26 computes the difference between the differencesignals FD0 and FD1 in units corresponding to each field.

Step ST6:

The comparison circuit 26 decides whether or not the difference computedat step ST5 is larger than a predetermined reference value, proceeds tothe processing of step ST7 when deciding that the difference signal islarger, and proceeds to the processing of step ST8 when not deciding so.

Step ST7:

The comparison circuit 26 makes the value of the comparison resultsignal COMP in the corresponding field period the logical value “0”.

Step ST8:

The comparison circuit 26 makes the value of the comparison resultsignal COMP in the corresponding field period the logical value “1”.

Step ST9:

The comparison circuit compares whether or not the generation of thecomparison result signal COMP is completed, proceeds to the processingof step ST10 when deciding that the generation is completed, and returnsto the processing of step ST6 when the generation is not completed.

Step ST10:

The judgment circuit 27 judges whether or not the video signalcorresponding to the luminance signal F0 is a film video signal and thesequence thereof based on the comparison result signal COMP from thecomparison circuit 26. Specifically, the judgment circuit 27 judges thatthe luminance signal F0 is a luminance signal of a film video signalwhen deciding that the comparison result signal COMP periodicallygenerates the pulse of the logical value “1” one time in five fields.

As explained above, according to the signal processing apparatus 20, asin the conventional case explained by using FIG. 11, it is not necessaryto provide the delay circuit for delaying the luminance signal F0 by theamount of two fields in addition to the delay circuit for delaying theluminance signal F0 by the amount of one field, therefore a reduction ofsize can be achieved.

Note that, in the above embodiment, the case where the processing shownin FIG. 3 was carried out by using the hardware shown in FIG. 1 wasexemplified, but it is also possible to perform the processing explainedby using FIG. 3 by executing the program describing routines shown inFIG. 3 by a CPU.

[Second Embodiment]

Below, an explanation will be given of a case where the signalprocessing apparatus 20 of the first embodiment is used for a DVD(digital versatile disk) player.

FIG. 4 is a functional block diagram of a DVD player 30 of the presentembodiment.

As shown in FIG. 4, the DVD player 30 has for example a DVD drive 1, anMPEG decoder (Moving Picture Expert Group) 2, a one-field delay circuit3, a selector circuit 4, a time axis compression circuit 5, a time axiscompression circuit 6, a selector circuit 7, a D/A conversion circuit 8,a controller 9, a one-field delay circuit 21, a subtractor circuit 22,an adder circuit 23, a one-field delay circuit 24, a one-field delaycircuit 25, and a comparison circuit 26.

In FIG. 4, the one-field delay circuit 21, the subtractor circuit 22,the adder circuit 23, the one-field delay circuit 24, the one-fielddelay circuit 25, and the comparison circuit 26 given the same notationsas those of FIG. 1 are the same as those explained in the firstembodiment.

The DVD drive 1 outputs the video signal reproduced from the DVD to theMPEG decoder 2.

The MPEG decoder 2 decodes the video signal input from the DVD drive 1,outputs the luminance signal F0(Y) of the video signal obtained by thedecoding to the one-field delay circuit 21, and outputs a verticalsynchronization signal VSNC to the subtractor circuit 22, the addercircuit 23, the one-field delay circuit 24, the one-field delay circuit25, and the comparison circuit 26.

The one-field delay circuit 21 outputs the luminance signal F1, obtainedby delaying the luminance signal F0(Y) shown in FIG. 5A input from theMPEG decoder 2 by an amount of one field, to the subtractor circuit 22,the one-field delay circuit 3, and the time axis compression circuit 5.

The one-field delay circuit 3 outputs the luminance signal F2, obtainedby further delaying the luminance signal F1 input from the one fielddelay circuit 21 by an amount of one field, to the selector circuit 4.

The subtractor circuit 22, the adder circuit 23, the one-field delaycircuit 24, the one-field delay circuit 25, and the comparison circuit26 operate by using the vertical synchronization signal VSNC from theMPEG decoder 2 as a reference. The operation content is the same as thatexplained in the first embodiment. Note that the comparison circuit 26outputs the comparison result signal COMP shown in FIG. 5F to thecontroller 9.

The selector circuit 4 outputs a signal S4 shown in FIG. 5H, selected asshown in FIG. 5G by a selection signal S9 a from the controller 9between the signal of the field in the not delayed luminance signal F0input from the MPEG decoder 2 and the signal of the field in theluminance signal F2 delayed by 2 fields input from the one-field delaycircuit 3, to the time axis compression circuit 6.

As shown in FIG. 5G, the selector circuit 4 repeats the signal selectionby the pattern of F2, F0, F2, F0, and F0 for five continuous fields.

The time axis compression circuit 5 outputs a signal S5 obtained bycompressing the luminance signal F1 delayed by one field input from theone-field delay circuit 21 in time axis for each line signal based onthe control signal S9 c from the controller 9 to the selector circuit 7.

The selector circuit 7 generates a progressive signal S7 comprised ofsignals of lines selected based on a selection signal S9 d shown in FIG.5J from the controller 9 between a signal S5 and a signal S6 and outputsthis to the D/A conversion circuit 8.

The selector circuit 7 performs the selection operation of the linesignal during the period where for example the selection signal S9 dshown in FIG. 5J indicates the logical value “1”.

The D/A conversion circuit 8 converts the digital progressive signal S7to an analog progressive signal S8 and outputs it.

FIG. 6 to FIG. 9 are views for explaining timings of the input of theline signal in the field of the luminance signal F1, the output of theline signal in the signal S5, the input of the line signal in the fieldof the signal S4, and the output of the line signal in the signal S6 inthe time axis compression circuit 5 and the time axis compressioncircuit 6, and the progressive signal S7 generated by the selectorcircuit 7.

Here, FIG. 7 to FIG. 9 show portions of periods T1 to T3 in FIG. 6enlarged.

Note that, in these figures, for convenience of the explanation, it isassumed that each field is comprised of six lines.

The time axis compression circuit 5, in the period T1 of the odd fieldshown in FIG. 6 and FIG. 7, writes the data of the first line of thesignal F1 output from the one-field delay circuit 3, compresses it inthe time axis, and outputs the result to the selector circuit 7.

The time axis compression circuit 6 compresses the data of the secondline supplied from the selector circuit 4 and outputs the result to theselector circuit 7 after the time axis compression circuit 5 outputs thedata of the first line.

Below, in the same way, the time axis compression circuit 5 sequentiallycompresses the data of the third line and the fifth line and outputs theresult, and the time axis compression circuit 6 sequentially compressesand outputs the data of the fourth line and the sixth line.

The selector circuit 7 alternately selects the data of lines output fromthe time axis compression circuit 5 and the time axis compressioncircuit 6 and outputs them to the D/A conversion circuit 8 in thesequence of the first line, the second line, the third line, the fourthline, the fifth line, and the sixth line. The D/A conversion circuit 8performs the D/A conversion for the input data and outputs the result.

As shown in FIG. 6 and FIG. 8, in a period T2 of an even field, the timeaxis compression circuit 5 sequentially compresses the data of thesecond line, the fourth line, and the sixth line, and outputs theresult, and the time axis compression circuit 6 sequentially compressesand outputs the data of the first line, the third line, and the fifthline.

The selector circuit 7 alternately selects the outputs of the time axiscompression circuit 5 and the time axis compression circuit 6 also inthis case and thereby sequentially selects and outputs the data of thefirst line to the sixth line.

In a period T3 of the odd field shown in FIG. 6 and FIG. 9, the sameprocessing as that in the period T1 is executed.

Below, an explanation will be given of an example of the operation ofthe DVD player 30 shown in FIG. 4.

The DVD drive 1 outputs the video signal reproduced from the DVD to theMPEG decoder 2.

Then, the MPEG decoder 2 decodes the video signal input from the DVDdrive 1 and outputs the luminance signal F0(Y) of the video signalobtained by the decoding to the one-field delay circuit 21.

Then, the one-field delay circuit 21 generates the luminance signal F1obtained by delaying the luminance signal F0(Y) shown in FIG. 5A inputfrom the MPEG decoder 2 by an amount of one field and outputs this tothe subtractor circuit 22, the one-field delay circuit 3, and the timeaxis compression circuit 5.

Then, the one-field delay circuit 3 generates the luminance signal F2obtained by delaying the luminance signal F1 input from the one-fielddelay circuit 21 by an amount of one field and outputs this to theselector circuit 4.

Further, the subtractor circuit 22, the adder circuit 23, the one-fielddelay circuit 24, the one-field delay circuit 25, and the comparisoncircuit 26 perform an operation the same as that of the signalprocessing apparatus 20 explained in the first embodiment, and thecomparison result signal COMP shown in FIG. 5F is output from thecomparison circuit 26 to the controller 9.

Then, the controller 9 generates selection signals S9 a and S9 d andcontrol signals S9 b and S9 c as mentioned before and outputs them tothe selector circuit 4, the time axis compression circuit 5, the timeaxis compression circuit 6, and the selector circuit 7.

Due to this, the selector circuit 4 outputs the signal S4 shown in FIG.5H, selected as shown in FIG. 5G by the selection signal S9 a betweenthe signal of the field in the luminance signal F0 and the signal of thefield in the luminance signal F2, to the time axis compression circuit6.

Then, the time axis compression circuit 6 outputs the signal S6,obtained by compressing the signal S4 input from the selector circuit 4in time for each line signal, to the selector circuit 7 based on thecontrol signal S9 b.

Further, the time axis compression circuit 5 outputs he signal S5obtained by compressing the luminance signal F1 in time axis for eachline signal to the selector circuit 7 based on the control signal S9 c.

Then, the selector circuit 7 generates the progressive signal S7comprised of the signal of each line selected between the signal S5 andthe signal S6 based on the selection signal S9 d and outputs this to theD/A conversion circuit 8.

Then, the D/A conversion circuit 8 converts the digital progressivesignal S7 to the analog progressive signal S8 and outputs this.

[Third Embodiment]

The above series of processing can be executed by hardware too, but canalso be executed by software. In this case, for example, the DVD playeris configured by a personal computer as shown in FIG. 10.

In FIG. 10, a CPU (central processing unit) 41 executes various types ofprocessing according to a program stored in a ROM (read only memory) ora program loaded into a RAM (random access memory) 43 from a memory unit48. The program corresponds to the program of the present invention anddescribes for example various routines including the routines shown inFIG. 3.

The RAM 43 appropriately stores also data required when executingvarious types of processings by the CPU 41.

The CPU 41, the ROM 42, and the RAM 43 are connected to each other via abus 44. This bus 44 also has an input/output interface 45 connected toit.

The input/output interface 45 has an input portion 46 configured by akeyboard, mouse, etc., a display configured by a CRT, LCD, etc., anoutput portion configured by a speaker, etc., a memory unit 48configured by a hard disk etc., and a communication unit 49 configuredby a modem, terminal adapter, etc. connected to it. The communicationunit 49 performs the communication processing via a network, includingthe Internet.

The input/output interface 45 has a drive 50 connected to it accordingto need; a magnetic disk 61 an optical disk 62, an opto-magnetic disk63, a semiconductor memory 64, etc. is suitably loaded in it, and acomputer program read out from these is loaded in the memory unit 48according to need.

When the above series of processing is executed by software, the programcomprising the software is loaded into a computer of dedicated hardware,or for example a general purpose personal computer capable of executingvarious types of functions by loading various types of programs, fromthe network or a recording medium.

This recording medium is configured by not only a package mediumdistributed for providing the program to users separately from theapparatus, comprising a magnetic disk 61 (including floppy disk)recording the program therein, an optical disk 62 (including CD-ROM(compact disk-read only memory), DVD (digital versatile disk)),opto-magnetic disk 63 (including MD (Mini-Disk)), a next generationlarge capacity optical disk with a finer track pitch than a DVD, calleda “Blue-Ray disk” (not illustrated), or a semiconductor memory 64 asshown in FIG. 10, but also a ROM 42 recording the program, a hard diskincluded in the memory unit 48, etc. provided to the users in a stateinstalled in the apparatus in advance.

Note that, in the present description, the step of writing the programrecorded in the recording medium includes not only processing performedin a time sequence along the written sequence, but also processing notnecessarily carried out in a time sequence, that is, executed inparallel or individually.

The present invention is not limited to the above embodiments.

For example, in the above embodiments, as the module signals of thefourth to the sixth aspects of the inventions, the signals of fields ofluminance signals were exemplified, but the invention is not limited tothis. The present invention can also be applied to a case where variousmodule signals other than field signals are used. In this case, as thedetected signal, use is made of a signal in which there is a pattern oftwo coinciding module signals located at two sides sandwiching apredetermined module signal at a predetermined position in apredetermined number of continuous module signals.

As explained above, according to the first to the third aspects of theinventions, a signal processing apparatus capable of being reduced insize when detecting a video signal in which there is a pattern of twocoinciding fields located at two sides sandwiching a predetermined fieldat a predetermined position in a predetermined number of continuousfields, a method of the same, and a program of the same can be provided.

Further, according to the fourth to the sixth aspects of the inventions,a signal processing apparatus capable of being reduced in size whendetecting a detected signal comprised of a plurality of module signalswherein there is a pattern of two coinciding module signals located attwo sides sandwiching a predetermined module signal at a predeterminedposition in a predetermined number of continuous module signals can beprovided.

Industrial Capability

The present invention can be utilized in for example the case of judgingthe format of an image signal.

1. A signal processing apparatus comprising: a first delaying means fordelaying a luminance signal by an amount of one field; a processingmeans for generating a difference signal indicating a difference betweensaid luminance signal delayed by an amount of one field by said firstdelaying means and a not delayed luminance signal for each field; asecond delaying means for delaying said difference signal generated bysaid processing means by an amount of one field; and a judging means forcomparing the difference signal generated by said processing means andsaid difference signal delayed by an amount of one field by said seconddelaying means and judging the format of said luminance signal based onthe result of said comparison.
 2. A signal processing apparatus as setforth in claim 1, wherein said processing means finds a difference inunits of pixel data in each field and generates said difference signaldefining the value obtained by cumulatively adding one-field amounts ofthe differences as the difference of the fields.
 3. A signal processingapparatus as set forth in claim 2, wherein said judging means judgesthat said luminance signal is a film video signal if the differencesignal generated by said processing means and said difference signaldelayed by an amount of one field by said second delaying means coincideat an interval corresponding to the time of a predetermined number offields based on the result of said comparison.
 4. A signal processingapparatus as set forth in claim 3, wherein said film video signal is afilm video signal in which there is a pattern of coinciding luminancesignals of two fields located at two sides sandwiching a luminancesignal of a predetermined field at a predetermined position in apredetermined number of continuous fields.
 5. A signal processingapparatus as set forth in claim 1, further comprising: a third delayingmeans for delaying said luminance signal delayed by an amount of onefield by said first delaying means further by the amount of one fieldand a signal generating means for generating a progressive signal bycombining line signals in said not delayed luminance signal, saidluminance signal delayed by said first delaying means, and saidluminance signal delayed by said third delaying means based on theresult of judgment of said judging means.
 6. A signal processing methodcomprising: a first step of delaying a luminance signal by an amount ofone field; a second step of generating a difference signal indicatingthe difference between said luminance signal delayed by an amount of onefield at said first step and a not delayed luminance signal for eachfield; a third step of delaying said difference signal generated at saidsecond step by an amount of one field; and a fourth step of comparingthe difference signal generated at said second step and said differencesignal delayed by an amount of one field at said third step and judgingthe format of said luminance signal based on the result of saidcomparison.
 7. A program executed by a signal processing apparatus,comprising: a first routine of delaying a luminance signal by an amountof one field; a second routine of generating a difference signalindicating the difference between said luminance signal delayed by anamount of one field in said first routine and a not delayed luminancesignal for each field; a third routine of delaying said differencesignal generated in said second routine by an amount of one field; and afourth routine of comparing the difference signal generated in saidsecond routine and said difference signal delayed by an amount of onefield in said third routine and judging the format of said luminancesignal based on the result of said comparison.
 8. A signal processingapparatus for detecting a detected signal comprised of a plurality ofmodule signals wherein there is a pattern of two coinciding modulesignals located at two sides sandwiching a predetermined module signalat a predetermined position in a predetermined number of continuousmodule signals, comprising: a first delaying means for delaying a signalunder detection by an amount of one module signal; a processing meansfor generating a difference signal indicating the difference betweensaid signal under detection delayed by an amount of one module signal bysaid delaying means and a not delayed signal under detection in units ofsaid module signal; a second delaying means for delaying the differencesignal generated by said processing means by an amount of one modulesignal; and a detecting means for comparing the difference signalgenerated by said processing means and said difference signal delayed byan amount of one module signal by said second delaying means anddetecting whether or not said signal under detection is said detectedsignal based on the result of the comparison.
 9. A signal processingmethod for detecting a detected signal comprised of a plurality ofmodule signals wherein there is a pattern of two coinciding modulesignals located at two sides sandwiching a predetermined module signalat a predetermined position in a predetermined number of continuousmodule signals, comprising: a first step of delaying a signal underdetection by an amount of one module signal; a second step of generatinga difference signal indicating the difference between said signal underdetection delayed by an amount of one module signal at said first stepand a not delayed signal under detection in units of said module signal;a third step of delaying said difference signal generated at said secondstep by an amount of one module; and a fourth step of comparing saiddifference signal generated at said second step and said differencesignal delayed by an amount of one module signal at said third step anddetecting whether or not said signal under detection is said detectedsignal based on the result of the comparison.
 10. A program, executed bya signal processing apparatus, for detecting a detected signal comprisedof a plurality of module signals wherein there is a pattern of twocoinciding module signals located on two sides sandwiching apredetermined module signal at a predetermined position in apredetermined number of continuous module signals, comprising: a firstroutine of delaying a signal under detection by an amount of one modulesignal; a second routine of generating a difference signal indicatingthe difference between said signal under detection delayed by an amountof one module signal in said first routine and said not delayed signalunder detection in units of said module signal; a third routine ofdelaying said difference signal generated in said second routine by anamount of one module; and a fourth routine of comparing said differencesignal generated in said second routine and said difference signaldelayed by an amount of one module signal in said third routine anddetecting whether or not said signal under detection is said detectedsignal based on the result of the comparison.